TTL components are extensively used in standard electronic boards while CMOS technology has found wide acceptance in the implementation of complex logic/memory functions of semiconductor chips. A major concern in the high and low voltage levels in TTL circuits which are different from those in CMOS circuits. By way of example, a typical TTL circuit operates with standard high and low voltages of approximately 2.2 and 0.8 volts, respectively, while typical CMOS circuits operate with high and low voltages of 5 and 0 volts, respectively. As a result, in order to couple the output of a TTL circuit to the input of a CMOS circuit, a converting circuit is commonly used to change the logic levels. Conversion from TTL levels to CMOS levels is conventionally realized with CMOS on-chip receivers. These CMOS receiver circuits suffer from a high DC current flowing in the input branch when the input TTL signal is at a high level, as will be illustrated in conjunction with the conventional TTL/CMOS receiver circuit 10 shown in FIG. 1.
As apparent from FIG. 1, the first stage consists of an inverter I0 that amplifies the logic input signal V.sub.in at the input terminal 11. The amplified signal is latched in latch 12 which includes two inverters I1 and I2 connected in series, and whose respective inputs and outputs are interconnected. Complementary signal phases are generated and enforces at full-swing levels on nodes A and B. Finally, buffered true and complement output signals V.sub.out and V.sub.out, are delivered via inverting buffers I3 and I4 at the output terminals 13 and 14, respectively. Inverters and buffers are conventionally comprised of a pair of complementary FET devices as illustrated in FIG. 1. These circuits are biased between a first supply voltage V.sub.H, typically, 5 volts, and a second supply voltage, typically ground (GND).
The main drawback of this conventional solution occurs when the input signal V'.sub.in is at its TTL high level, i.e., approximately 2.2 Volts, which is not sufficient to completely turn off PFET P'0 of inverter I0 when NFET N'0 is saturated. In this instance, the gate to source voltage V.sub.gs (P'0) is approximately 2.8 V. As a result, a few milliamps of DC current are produced in the quiescent state as they flow through the two FET devices.
In addition, the conventional circuit of FIG. 1 is recognized to exhibit large delay variations (or dispersions) between the input and output signals which, in turn, results in a distinct level of asymmetry between the signals representing the two phases of the output signal for both rising and fall transitions of the input signal.